VLSI Implementation and design of Carry Skip Adder using Reversible gates for Arithmetic applications

Electronics and Instrumentation Engineering

In this paper, we present a Carry Skip Adder (CSKA) structure using reversible logic that has a higher speed yet lower energy consumption compared with the existing system. The existing system makes use of AND-OR Invert (AOI) and OR-AND Invert (OAI) compound gates for the skip logic with both fixed stage size and variable stage size. In the proposed system, low complexity Carry Skip Adder is designed by using reversible gates. Reversible gate having the properties of moderate delay, low complexity and low quantum cost is chosen especially as New Toffoli gate or Peres gate. This gate acts as universal reversible three bit gate that swaps last two bits if first bit is high. If it is set, it inverts or remains same during the operations. Each and every block in skip adder is modified as proposed gate. By this process, full adder is designed by New Toffoli gate or Peres gate and then it is extended to RCA and incrementation blocks. The proposed structures are assessed by comparing their propagation delay, power consumption and area parameters with those of other adders. Simulation on the proposed CSKA reveal reduction in the power consumption and propagation delay but the area remains almost same as the existing system. Compared with the latest works in this field, the proposed system is having a reasonably high speed.

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