IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA

Electronics and Communication Engineering

Low-precision arithmetic operations to accelerate deep-learning applications on field- programmable gate arrays (FPGAs) have been studied extensively, because they offer the potential to save silicon area. However, these benefits come at the cost of a decrease in accuracy. Neural network-based methods for image processing are becoming widely used in practical applications. Modern neural networks are computationally expensive and require specialized hardware, such as graphics processing units. Since such hardware is not always available in real life applications, there is a compelling need for the design of neural networks for mobile devices. Mobile neural networks typically have reduced number of parameters and require a relatively small number of arithmetic operations. However, they usually still are executed at the software level and use floating-point calculations. The use of mobile networks without further optimization may not provide sufficient performance when high processing speed is required, for example, in real-time video processing (30 frames per second). In this study, we suggest optimizations to speed up computations in order to efficiently use already trained neural networks on a mobile device.

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