DESIGN AND IMPLEMENTATION OF LOW POWER DYNAMIC LATCH COMPARATOR

Praveen Kumar N.C; Ananth. V. Naik; Bharath Kumar. S; Gayathri K.M

DESIGN AND IMPLEMENTATION OF LOW POWER DYNAMIC LATCH COMPARATOR

February 2017

Volume-1, Issue-5, 2016

Paper ID: C-1406

ISSN: 2395-4396

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Abstract & Details

Research Area

Electronics and Communication Engineering

Conference

National Conference on "Recent Advances in Materials Science & its Applications" & "Recent Trends in Electrical, Electronics, Computing and Information Technology"

Keywords

Analog to Digital Converter. CMOS process low power comparator

Abstract

In this article we composed a low power comparator for a use of low power simple to advanced converters. In advanced correspondence and sign preparing frameworks, ADC's assume a noteworthy part. To show signs of improvement execution of ADC's we outlined low power utilization comparator. The proposed comparator has a best execution than past best outlines. It is outlined in Cadence 180nm CMOS process and 90nm CMOS process with supply voltages from 0.8V to 1.8V. This outline works with up to clock recurrence of 900MHz and information recurrence of 10Hz to 5GHz.

License

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author Information

#	Name	Institute / Affiliation
1	Praveen Kumar N.C	Jain University, Bangalore
2	Ananth. V. Naik	Jain University, Bangalore
3	Bharath Kumar. S	Jain University, Bangalore
4	Gayathri K.M	Jain University, Bangalore

How to Cite

Use the following formats to cite this article in your research.

APA Style

Kumar N.C, Praveen, V. Naik, Ananth., Kumar. S, Bharath, & K.M, Gayathri (2017). DESIGN AND IMPLEMENTATION OF LOW POWER DYNAMIC LATCH COMPARATOR. International Journal of Advance Research and Innovative Ideas In Education, 1(5), 76-83.

MLA Style

Kumar N.C, Praveen, et al. "DESIGN AND IMPLEMENTATION OF LOW POWER DYNAMIC LATCH COMPARATOR." International Journal of Advance Research and Innovative Ideas In Education, vol. 1, no. 5, 2017, pp. 76-83.

IEEE Style

Praveen Kumar N.C, Ananth. V. Naik, Bharath Kumar. S, and Gayathri K.M, "DESIGN AND IMPLEMENTATION OF LOW POWER DYNAMIC LATCH COMPARATOR," International Journal of Advance Research and Innovative Ideas In Education, vol. 1, no. 5, pp. 76-83, 2017.

Vancouver Style

Kumar N.C Praveen, V. Naik Ananth., Kumar. S Bharath, K.M Gayathri. DESIGN AND IMPLEMENTATION OF LOW POWER DYNAMIC LATCH COMPARATOR. International Journal of Advance Research and Innovative Ideas In Education. 2017;1(5):76-83.

Harvard Style

Kumar N.C, Praveen, V. Naik, Ananth., Kumar. S, Bharath, & K.M, Gayathri (2017) 'DESIGN AND IMPLEMENTATION OF LOW POWER DYNAMIC LATCH COMPARATOR', International Journal of Advance Research and Innovative Ideas In Education, 1(5), pp. 76-83.

Chicago Style

Kumar N.C, Praveen, et al. "DESIGN AND IMPLEMENTATION OF LOW POWER DYNAMIC LATCH COMPARATOR." International Journal of Advance Research and Innovative Ideas In Education 1, no. 5 (2017): 76-83.

Turabian Style

Kumar N.C, Praveen, et al. "DESIGN AND IMPLEMENTATION OF LOW POWER DYNAMIC LATCH COMPARATOR." International Journal of Advance Research and Innovative Ideas In Education 1, no. 5 (2017): 76-83.